Silicon-on-insulator (SOI) technology is becoming of increasing importance in the field of integrated circuits. SOI technology deals with the formation of transistors in a layer of semiconductor material which overlies an insulating layer; the most common embodiment of SOI structures is a single crystal layer of silicon which overlies a layer of silicon dioxide. High performance and high density integrated circuits are achievable using SOI technology because of the reduction of parasitic elements present in integrated circuits formed in bulk semiconductor. For example, for an MOS transistor formed in bulk, parasitic capacitance is present at the junction between the source/drain regions and the underlying substrate, and the possibility of breakdown of the junction between source/drain regions and the substrate region also exists. A further example of parasitic elements are present for CMOS technology in bulk, where parasitic bipolar transistors formed by n-channel and p-channel transistors in adjacent wells can give rise to latch-up problems. Since SOI structures significantly alleviate the parasitic elements, and increase the junction breakdown tolerance of the structure, the SOI technology is well-suited for high performance and high density integrated circuits.
It should be noted that a similar technology to SOI is the silicon-on-sapphire (SOS) technology, which provides similar benefits as those discussed relative to SOI technology above. It should be noted that the invention to be disclosed herein is applicable to SOS structures, as well.
The underlying insulator film in an SOI structure presents certain problems relative to the transistor characteristics, however. In bulk transistors, electrical connection is easily made via the substrate to the body node of an MOS transistor. The relatively fixed bias of the body node provides for a stable threshold voltage relative to the drain-to-source voltage. However, conventional SOI transistors have the body node (i.e., the undepleted volume within the body region) electrically floating, as the body node is isolated from the substrate by the underlying insulator film. Under sufficient drain-to-source bias (even, in some cases, with zero gate bias), impact ionization can generate electron-hole pairs near the drain which, due to the majority carriers traveling to the body node while the minority carriers travel to the drain, cause a voltage differential between the body node and the source of the transistor. This voltage differential lowers the effective threshold voltage and increases the drain current, resulting in the well known "kink" in the drain current-voltage characteristic.
Furthermore, the SOI transistor includes a parasitic "back channel" transistor, with the substrate as the gate and the insulator film underlying the transistor as the gate dielectric. This back channel may provide a drain-source leakage path along the body near the interface with the buried insulator. In addition, the dielectrically isolated body node allows capacitive coupling between the body node and the gate, and diode coupling between the body node and the source and drain, to bias the body node and thus affect the threshold voltage. Each of these factors can contribute to undesirable performance shifts in the transistor relative to design, as well as to increased instability of the transistor operating characteristics.
It is therefore useful to provide electrical bias to the body node of a transistor. A useful body node bias, as in the bulk case, is to ohmically connect the body node to the source of the MOS transistor. This requires that the source node of the transistor be specified, and connection made thereto from the body node of the transistor. Prior methods for body-to-source node connection require specification of the mesa regions on the sides of the gate as drain and source relatively early in the fabrication process. An example of such a method is described in U.S. Pat. No. 4,974,051, issued Nov. 27, 1990, and assigned to Texas Instruments Incorporated, where the source is defined by dedicating a portion of the mesa adjacent to the gate to receive an implant of the same conductivity type as the body, and connecting this dedicated portion to the source via a refractory metal silicide.
In the manufacture of mask-programmable logic such as gate arrays, it is preferable that the routing be determined as late as possible in the fabrication process, providing maximum flexibility in the assignment of transistors to specific gates. In conventional gate arrays, the specification of which node of a transistor is to be the drain and which is to be the source would preferably be done at the mask levels of metal contacts and metal, as such mask levels are generally the levels at which the interconnection routing and gate utilization is performed.
It is therefore an object of this invention to provide an insulated-gate field effect transistor formed in a semiconductor region overlying an insulator, where specification of the drain and source nodes of the transistor may be done at a relatively late point in the fabrication process.
It is another object of this invention to provide such a transistor where such specification may be done at the metal contact mask level.
It is another object of this invention to provide such a transistor which can be fabricated in conjunction with silicide-cladding of the source and drain diffusions.
It is a further object of this invention to provide such a transistor which provides such contact without reducing the effective channel width of the transistor.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to this specification and the accompanying drawings.